In recent years, memory devices with a USB (Universal Serial Bus) memory, a flash memory card, or other such nonvolatile memories have been widely used for reasons of large capacity, nonvolatile property, and low power consumption.
A reliability of long-term data storage is required of these memory devices. In addition, demands for memory devices of larger capacity grow along with an increase in data size such as an image or a moving picture. Then, reduction of a process for a nonvolatile memory has been actively performed.
FIG. 33 is a circuit diagram illustrating the basic cell structure of a NAND nonvolatile memory. A nonvolatile memory (Nonvolatile memory) 90 has plural NAND cells (Cells) (memory transistors) 92 in a NAND cell group 91 connected in series.
Any NAND cell 92 is selected by a select gate (Select Gate) 93. Further, erasing is carried out for each NAND cell group 91. Each NAND cell 92 includes a control gate (Control Gate) 92a and a floating gate (Floating Gate) 92b. 
FIG. 34A and FIG. 34B illustrate how data is written/erased to/from a nonvolatile memory. FIG. 34A illustrates how data is written to the nonvolatile memory. The floating gate 92b is insulated from the control gate 92a and a substrate (Substrate) 92c through a gate oxide film (Gate oxide) 92d and assumed electrically floating.
However, if a high voltage is applied between the control gate 92a and the substrate 92c, charges may be injected to the floating gate 92b from the substrate 92c through the gate oxide film 92d due to FN (Fowler-Nordheim) tunnel phenomenon.
Since the floating gate 92b is in an electrically floating state, charges may be held even when the power is turned off. The injection of charges is generally called “write” or “program (Program)”.
Further, as illustrated in FIG. 34B, if a high-voltage is applied in an opposite direction to the write direction, the charges injected into the floating gate 92b may be similarly released to the substrate 92c through the gate oxide film 92d due to the FN tunnel phenomenon. The release of charges is generally called “clear” or “erase (Erase)”.
In general, the NAND nonvolatile memory is assumed in write state (logic “0”) when charges are injected and in erase state when charges are released (logic “1”). Accordingly, Japanese Laid-open Patent Publication No. 2007-164937 discusses a technique that a memory cell of nonvolatile semiconductor memory device stores one data value selected from the same number of data values as programming distribution ranges, the one data value being associated with the electrical attribute belonging to any one of the more than one programming distribution ranges.